1. Field of the Invention
The present invention relates to controlling access to memory, and more particularly, to a memory controller which writes data on memory using an address line.
2. Description of the Related Art
Recently, synchronous dynamic random access memories (SDRAMs), such as double data rate synchronous dynamic random access memories (DDR SDRAMs) or Rambus DRAMs, have been welcomed as next-generation DRAMs and are also expected to dominate the future RAM market due to their high-speed data accessibility.
FIG. 1 is a diagram illustrating a conventional method of controlling the access of a DDR SDRAM when writing data on or reading data from the DDR SDRAM. In particular, FIG. 1 shows a memory controller 100 and a memory module 110.
Referring to FIG. 1, the memory controller 100 includes an address latch (AL) 101, a memory address queue (MAQ) 102, a data latch (DL) 103, a read data queue (RDQ) 104, and a write data queue (WDQ) 105.
The address latch 101 latches address data input into the memory controller 100.
The memory address queue 102 sequentially stores the address data transmitted from the address latch 101 and keeps the address data at a state where the address data is to be output. The address data include column address data and row address data, and the column address data and the row address data are sequentially output via a 12-bit address line.
The data latch 103 latches data input into the memory controller 100 from a system, i.e., written data, or data transmitted to the system, i.e., read data.
The read data queue 104 sequentially stores data read by the memory module 110 and keeps the stored data in a state ready to be output to the data latch 103.
The write data queue 105 sequentially stores the data transmitted from the data latch 103 that is to be stored in the memory module 110 and keeps the stored data in a state ready to be output to the memory module 110.
The memory module 110 includes a column address data register (CA) 111 which interprets the column address data provided by the memory controller 100, a row address data register (RA) 112 which interprets row addresses, a memory cell (MC) 113 which is comprised of a matrix of addresses interpreted by the column address data register 111 and the row address data register 112, a read data buffer (RD) 114 which temporarily stores data read from the memory cell 113, and a write data buffer 115 which temporarily stores data to be written on the memory cell 113.
The operation of the memory controller 100 in a typical memory device is as follows.
Address data and data that are input from a predetermined element 160 of a system 150, such as an interface or a central processing unit (CPU) via a system bus 170 are sequentially latched by the address latch 101 and the data latch 103, respectively. The latched address data are divided into a column address and a row address, and then the column address and the row address are encoded separately. Thereafter, the encoded column address and the encoded row address are sequentially stored in an address queue, i.e., the memory address queue 102. An upper module 180, a lower module 190, and a system element 160 are coupled to system bus 170.
Depending on whether the current mode is a data write mode or a data read mode, different manners for transmitting data can be adopted. In a data read mode, full-byte (8-byte or 16-byte) data is transmitted from the memory module 110 to the memory controller 100. The transmitted data is sequentially stored in the read data queue 104 of the memory controller 100. Thereafter, the stored data is output to a system bus via the data latch 103 and then provided to a micom, thus completing the reading of the corresponding data from the memory module 110. Thereafter, the memory controller 100 returns to an idle state and waits for the next mode shift.
When the memory controller 100 enters into a data write mode, two different manners of writing data on a memory, i.e., a partial-write manner and a full-write manner, can be considered. In most data transmission cases, except for direct memory access (DMA) transmission, the partial-write manner is adopted. In the full-write manner, all the bytes of data are written on the memory together, while in the partial-write manner, data are written on the memory in groups of a predetermined number of bytes.
For example, in the case of correcting 1-byte data using the partial-write manner, the memory controller 100 receives 8-byte or 16-byte data read from a place in a memory module 110 where the 1-byte data to be corrected is written via a data line and corrects the 1-byte data included in the 8-byte or 16-byte data. Thereafter, the memory controller 100 transmits the corrected 8-byte or 16-byte data to the memory module 110. When the writing of data in the memory module 110 is complete, the memory controller 100 returns to an idle state.
FIGS. 2A–2E are timing diagrams of signals generated when controlling the access of memory using the conventional method of controlling the access of a DDR SDRAM when writing data on, or reading data from, the DDR SDRAM, shown in FIG. 1. Referring to FIGS. 2A–2E, according to a predetermined memory access protocol, a row address and a column address of a place from which data will be read and a row address and a column address of a place on which data will be written are transmitted via an address line in response to the clock signal (CLOCK) of FIG. 2A. The column addresses and the row addresses of FIG. 2B are transmitted in response to a column address strobe (CAS) signal of FIG. 2D and a row address strobe (RAS) signal of FIG. 2C, respectively. The clock signal (CLOCK), the CAS signal, and the RAS signal are generated from an upper module of a system and then transmitted to a memory controlling apparatus of a lower module through the memory data bus of FIG. 2E.
When there is not much of a time interval provided between the time when the column and row addresses used to read data from the memory module 110 are generated and the time when the column and row addresses used to write data in the memory module 110 are generated, data (read data) read from the memory module 110 and then transmitted from the memory module 110 to the memory controller 100 via a data line and data (write data) to be written in the memory module 110, transmitted from the memory controller 100 to the memory module 110, may be congested in the data line. In order to prevent such a bottle neck phenomenon from occurring in a single data line, a sufficient interval should be provided between the time when a memory is accessed in order to read data from the memory module 110 and the time when the memory is accessed in order to write data in the memory module 110. In other words, one should wait for a sufficient amount of time until a current memory accessing process in one of a data read mode or a data write mode is completed before launching a following memory accessing process in the other mode. However, the general performance of a system may deteriorate due to the delay in data processing. In addition, in order to correct a predetermined portion of data stored in the memory module 110 in a partial-write manner, data to be modified is read from the memory module 110 in a full-read cycle. However, the process of reading the data to be modified from the memory module 110 in a full-read cycle may cause problems with the control of a read-write cycle, as well as a substantial delay in the entire process, equivalent to the read cycle, that may lengthen other transmission processes' standby time.